Chisel 分配给 UInt 的各个位

Question

有人可以告诉我为什么下面的代码在Chisel中不会详细说明吗？看来我无法分配给 UInt 中的各个位。这是设计使然吗？

我确实看到了 Jack 对类似问题的回答，但是跨链位的以下逻辑类型在 SV 等中很常见并且很容易参数化。我可以看到创建 bool 向量以及各个位，但是仍然是如何回到 UInt 的问题...

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val rval = Wire(UInt(width=pwidth))
    rval(0) := in(0)
    for(w <- 1 until pwidth) {
      rval(w) := in(w) & !( in(w-1,0).orR() )
    }
    rval
  }

结果:

firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5808.4]: [module IuIrRename]  Expression T_1824 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5815.4]: [module IuIrRename]  Expression T_1826 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5822.4]: [module IuIrRename]  Expression T_1834 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5829.4]: [module IuIrRename]  Expression T_1842 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5834.4]: [module IuIrRename]  Expression T_1851 is used as a FEMALE but can only be used as a MALE.

Answer 1

经过继续实验(并查看生成的 Verilog 后)，以下代码相当于我正在寻找的代码:

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val ary = Wire(Vec(pwidth, Bool()))
    ary(0) := in(0)
    for(w <- 1 until pwidth) {
      ary(w) :=   in(w) && !( in(w-1,0).orR() )
    }
    val rval = Reverse(Cat(ary))
    rval
  }