我想尝试一下凿子中的 BlackBox 功能,但我收到以下警告信息,并且无法通过峰值/戳测试:
Total FIRRTL Compile Time: 237.8 ms
WARNING: external module "BlackBoxSwap"(swap:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
file loaded in 0.398085417 seconds, 25 symbols, 15 statements
源代码如下: 封装gcd
import chisel3._
import chisel3.util._
class BlackBoxSwap extends BlackBox with HasBlackBoxInline {
//class BlackBoxRealSwap extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle() {
//val clk = Input(Clock())
//val reset = Input(Bool())
val out2 = Output(UInt(16.W))
val out1 = Output(UInt(16.W))
val in2 = Input(UInt(16.W))
val in1 = Input(UInt(16.W))
})
//setResource("/real_swap.v")
setInline("BlackBoxSwap.v",
s"""
|module BlackBoxSwap (
| input [15:0] in1,
| input [15:0] in2,
| output [15:0] out1,
| output [15:0] out2
|);
|
|assign out1 = in2;
|assign out2 = in1;
|
|endmodule
""".stripMargin)
}
/**
* Compute GCD using subtraction method.
* Subtracts the smaller from the larger until register y is zero.
* value in register x is then the GCD
*/
class GCD extends Module {
val io = IO(new Bundle {
val value1 = Input(UInt(16.W))
val value2 = Input(UInt(16.W))
val loadingValues = Input(Bool())
val outputGCD = Output(UInt(16.W))
val outputValid = Output(Bool())
})
val x = Reg(UInt())
val y = Reg(UInt())
val swap = Module(new BlackBoxSwap)
when(x > y) { x := x - y }
.otherwise { y := y - x }
when(io.loadingValues) {
//x := io.value1
//y := io.value2
swap.io.in1 := io.value1
swap.io.in2 := io.value2
x := swap.io.out1
y := swap.io.out2
}
io.outputGCD := x
io.outputValid := y === 0.U
}
我检查了生成的RTL,看来是正确的。你能帮忙吗? 非常感谢!
最佳答案
在我看来,您正在尝试将 firrtl-interpreter 后端与 verilog 黑匣子一起使用。 verilog 黑盒只能与基于 verilog 的后端(例如 verilator 或 VCS)一起使用。如果您不清楚如何设置后端,请查看 chisel-template 中的示例。 。
有一种方法可以通过 firrtl-interpreter 后端使用黑盒模拟,但它需要您编写黑盒的 scala 实现。
关于chisel - chisel3 中的 BlackBox 功能,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/52365713/