自从我介绍 VHDL 类(class)以来已经 2 年了,我需要为我现在拥有的类(class)项目重新学习 VHDL。我开始构建一个 4 位 CLA 加法器,并且正在开发一个测试平台。我收到以下错误,我不知道为什么。我很确定它应该是这样的,但我的内存可能已经消失了。请帮我。
哦,作为引用,错误出现在第一个信号声明中
错误:COMP96_0019:adder_tb.vhd:(45、53):预期关键字“开始”。
错误:COMP96_0016:adder_tb.vhd:(45、54):预期设计单元声明。
我的测试台代码:
l
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity adder_tb is
end adder_tb;
architecture behavior of adder_tb is
-- Initialize the inputs/outputs of the unit to be tested
component cl_adder_4bit
port(
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0) ;
c_in : in std_logic := '0';
sum : out std_logic_vector(3 downto 0);
c_out : out std_logic
);
end component;
-- Signal declarations for stimulation
signal a : std_logic_vector(3 downto 0) := "0000"; //initial value will be 0;
signal b : std_logic_vector(3 downto 0) := "0000";
signal c_in : std_logic;
signal sum : std_logic_vector(3 downto 0);
signal c_out : std_logic;
begin
uut: cl_adder_4bit port map(
a <= a;
b <= b;
c_in <= c_in;
sum <= sum;
c_out <= c_out;
);
stimulate: process
begin
--This loop is for when c_in = 0
for i in 0 to 15 loop
-- This loop increments vector signal a, starting at b = 0x0
for j in 0 to 15 loop
wait for 5 ns; //wait for 5 ns
a <= a + 1;
end loop;
-- This loop increments vector signal b, starting at a = 0xF
for k in 0 to 15 loop
wait for 5 ns;
b <= b + 1;
end loop;
a <= a + 1;
b <= b + 1;
end loop;
--This second run is for when c_in is 1
for i in 0 to 15 loop
c_in <= '1';
-- This loop increments vector signal a, starting at b = 0x0
for j in 0 to 15 loop
wait for 5 ns; //wait for 5 ns
a <= a + 1;
end loop;
-- This loop increments vector signal b, starting at a = 0xF
for k in 0 to 15 loop
wait for 5 ns;
b <= b + 1;
end loop;
a <= a + 1;
b <= b + 1;
end loop;
end process;
end adder_tb;
最佳答案
怎么样
signal a : std_logic_vector(3 downto 0) := "0000"; //initial value will be 0;
应使用 VHDL 注释指示:
signal a : std_logic_vector(3 downto 0) := "0000"; -- initial value will be 0;
或者你的评论无论如何都是多余的。
逗号作为分隔符,您可以在端口映射中关联元素:
uut: cl_adder_4bit port map(
a <= a;
b <= b;
c_in <= c_in;
sum <= sum;
c_out <= c_out;
);
应该:
uut: cl_adder_4bit port map(
a => a,
b => b,
c_in => c_in,
sum => sum,
c_out => c_out
);
另一个不正确的注释定界:
wait for 5 ns; //wait for 5 ns
应该:
wait for 5 ns; -- wait for 5 ns
(以上两处)
架构的结束声明:
end adder_tb;
应该是:
end architecture;
或者
end architecture behavior;
或者
end behavior;
然后因为您使用的是加法运算符,您需要一个带有适当包的 use 子句,在这种情况下,它看起来应该是 Synopsys 的 std_logic_unsigned (in) 方便地隐藏在库 ieee 中:
(在您的设计文件的顶部):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
关于compiler-errors - 初学者的 VHDL 错误,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/26949162/