decimal - 什么 VHDL 库用于十进制模数

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity two_number_split is
    Port ( number  : in  integer range 0 to 99;
           position0 : out  STD_LOGIC_VECTOR (3 downto 0);
           position1 : out  STD_LOGIC_VECTOR (3 downto 0));
end two_number_split;

architecture Behavioral of two_number_split is
    signal pos0, pos1 : STD_LOGIC_VECTOR(3 downto 0);
begin
    convert: process(number, pos0, pos1)
    begin
            pos1 <= number/10;
            pos0 <= number mod 10;
            position0 <= std_logic_vector(pos0);
            position1 <= std_logic_vector(pos1);
    end process convert;

end Behavioral;

错误:

ERROR:HDLCompiler:1638 - "C:\Users\XXX\Documents\SS\ISE_Ex\seven_segment\two_numbers.vhd" Line 19: found '0' definitions of operator "/", cannot determine exact overloaded matching definition for "/"
ERROR:HDLCompiler:1638 - "C:\Users\XXX\Documents\SS\ISE_Ex\seven_segment\two_numbers.vhd" Line 20: found '0' definitions of operator "mod", cannot determine exact overloaded matching definition for "mod"

我想我只是使用了错误的库。有什么建议吗？我已经尝试了上面列出的库的所有组合，但不确定发生了什么。

Answer 1

可以修改pos0和pos1的声明为整数类型，计算后转换为BCD表示。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity two_number_split is
    port ( 
        number:     in   integer range 0 to 99;
        position0:  out  std_logic_vector (3 downto 0);
        position1:  out  std_logic_vector (3 downto 0)
    );
end two_number_split;

architecture Behavioral of two_number_split is
    signal pos0, pos1 : natural range 0 to 9; -- std_logic_vector(3 downto 0);
begin
    convert: process(number, pos0, pos1)
    begin
            pos1 <= number/10;
            pos0 <= number mod 10;
            position0 <= std_logic_vector(to_unsigned(pos0,position0'LENGTH)); 
            -- was <= std_logic_vector(pos0);
            position1 <= std_logic_vector(to_unsigned(pos1,position1'LENGTH));
            -- was <= std_logic_vector(pos1);
    end process convert;

end Behavioral;

它使用to_unsigned 将十进制数字值pos1 和pos0 转换为unsigned数组类型。返回的 unsigned 数组长度由第二个参数指定，它可以只是一个文字。

您可以使用unsigned 作为position0 和position1 的类型，并为每个赋值保存类型转换。

这里的想法有三个方面:可读性，使用具有兼容左右参数和返回值的运算符函数，以及使用 integer 乘法运算符比 unsigned 运营商。 number 的自然范围隐含了无符号运算。

这个例子有效:

但不是特别适合合成 - 有两个乘法运算符。如果您需要合成某些东西，请参阅 Convert 8bit binary number to BCD in VHDL获取有关如何避免七位乘法运算符的灵感。