verilog - 即使条件成立，我的代码也不会进入下一个状态

Question

我必须在 7 段 LED 上显示一条消息和一个计时器。因此，我通过使用多路复用器来管理此操作，并在一种状态下显示消息“Hi”，然后一段时间后，当计数器达到 7500 时，它应该停止显示“Hi”并开始显示计时器。

问题是它只显示“Hi”并且不会从那里向前移动。

localparam [1:0]
                    idle = 2'b00,
                    starting = 2'b01,
                    time_it = 2'b10,
                    done = 2'b11;

reg state_reg, state_next;
reg [12:0] count_reg, count_next; //**change for simulation

always @ (posedge clock or posedge reset)
begin
    if(reset)
        begin 
            state_reg <= idle;
            count_reg <= 0;
        end
    else
        begin
            state_reg <= state_next;
            count_reg <= count_next;
        end
end
always @ (*)
begin
state_next = state_reg; //default state stays the same
count_next = count_reg;

case(state_reg)
    idle:
        begin
            //DISPLAY HI HERE
            sel = 2'b00;
            if(start)
            begin
                count_next = random; //get the random number from LFSR module
                state_next = starting;
            end
        end
    starting:
        begin
            if(count_next == 7500) 
            begin                           //and starting from 'rand' ensures a random delay
                outled = 1'b1; //turn on the led 
                state_next = time_it; //go to next state
            end

            else
                count_next = count_reg + 1; 
        end     
    time_it:
        begin
                sel = 2'b01; //start the timer
                state_next = done;                  
        end

    done:
        begin
            if(stop)
                begin
                    sel = 2'b10; //stop the timer
                    outled = 1'b0;
                end
        end

    endcase

case(sel)
    2'b00: //hi
    begin
        go_start = 0; //make sure timer module is off
        regd0 = 4'd12; 
        regd1 = 4'd10;
        regd2 = 4'd11;
        regd3 = 4'd12;
    end

    2'b01: //timer
    begin

        go_start = 1'b1; //enable start signal to start timer
        regd0 = reg_d0; //get values from stopwatch module
        regd1 = reg_d1; //get values from stopwatch module
        regd2 = reg_d2; //get values from stopwatch module
        regd3 = reg_d3; //get values from stopwatch module
    end

    2'b10: //stop timer
    begin
        go_start = 1'b0;
    end

    default:
    begin
        regd0 = 4'bx;
        regd1 = 4'bx;
        regd2 = 4'bx;
        regd3 = 4'bx;
    end
endcase         
end

现在在模拟中，case 保持在 00 并且不会改变，即使它被告知在 time_it 状态下这样做。由于 sel 不会改变，因此 go_start 未启用，这就是计时器从未打开的原因。为什么它保留在 sel=00 中？

Answer 1

将状态寄存器从 1 位宽更改为 2 位宽:

reg [1:0] state_reg, state_next;