warnings - 晶格钻石 : Setting up a clock

Question

我正在学习 Verilog 并使用 CPLD，但我陷入了困境。我编写的代码会切换 LED，但在综合过程中我不断收到警告。

//toggles LED on and off after 1000000 clock cycles

module LEDON(
LED,
clk
);

output LED;
reg LED;

input clk ;
wire clk;

reg [31:0] count;
wire count_max = 32'd1_000_000;

assign count_nxt = (count >= count_max) ? 32'd0 : count + 32'd1;
assign led_state_nxt = (count == count_max) ? ~LED : LED;

always @(posedge clk)

begin
    count <= count_nxt;
    LED <= led_state_nxt;

end

endmodule

我收到这些警告:

@W: MT420 |Found inferred clock LEDON|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk"
WARNING - map: C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.lpf (4): Error in FREQUENCY NET "clk" 2.080000 MHz ;
WARNING - map: Preference parsing results: 1 semantic error detected
WARNING - map: There are errors in the preference file, "C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.lpf".
WARNING - map: There are semantic errors in the preference file, "C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.prf".

我的 LPF 文件如下所示:

BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "LED" SITE "41" ;
FREQUENCY NET "clk" 2.08 MHz ;

那么有人知道如何修复这些时钟警告吗？

Answer 1

我不确定这一行是否:“wire count_max = 32'd1_000_000;”是可合成的。除了在仿真中之外，它可能会被忽略(这可能取决于您的工具链 - 它对于 ASIC 来说是不可综合的，但对于 FPGA 来说......也许!!)。

行 count>= count_max 正在将 count 与 0 进行比较(而不是 count max)，因此这将被优化掉(请参阅警告)。这就是为什么它能够合成但没有做任何事情。

有多种解决方案。 1) 使用参数代替(就像 C++ 中的 const 或 C 中的#define):

parameter count_max = 32'd1_000_000;

2)只需使用较小的计数器并在溢出时切换

reg [16:0] count; // counts 131,072 cycles

assign led_next = (count == 0 ? ~LED : LED);
always @(posedge clk)
begin
    count <= count + 1;
    LED <= led_next;
end