arrays - 数组元素之和 VHDL

Question

我是 VHDL 新手，我搜索了整个互联网，但没有找到任何对我有帮助的东西!

我正在尝试添加数组的元素(32 个元素!)，所以我不能只写 例如 s <= s(0) + s(1) + s(3) ... s(5) + ....s(32)

我如何概括这样的计算？ 或者我做错了什么？

我的代码(在模拟中不起作用)是.. (仅适用于 5 个元素....)

library IEEE;
library work;
library std;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;

entity main is Port (
    EIN   : in std_logic;
    AUS_1 : out std_logic_vector(3 downto 0));
end main;

architecture Behaviour of main is

    type Cosinus is array (0 to 4) of std_logic_vector(3 downto 0); 
    type Sinus is array (0 to 4) of std_logic_vector(3 downto 0); 

    Signal SumSin :std_logic_vector(3 downto 0);

begin

    main : process(Ein)
        variable Cos : Cosinus;   
        variable Sin : Sinus;
    begin

        if( Ein='1' )  then
            sin(0) := "0011";
            sin(1) := "0001";
            sin(2) := "1010";
            sin(3) := "1111";
            sin(4) := "1110";

            for n in 0 to 4 loop
                SumSin <= SumSin + Sin(n);               
            end loop;
        else 
            sin(0) := "1011";
            sin(1) := "0101";
            sin(2) := "1000";
            sin(3) := "1001";
            sin(4) := "1100";

            for n in 0 to 4 loop
                SumSin <= SumSin + Sin(n);                         
            end loop;
        end if;
    end process;

    Aus_1 <= SumSin;    
end Behaviour;

我将不胜感激

Answer 1

首先... Don't use std_logic_arith.

然后，使用一个变量作为运行总和，然后将其分配给一个信号:

 ...
 main : process(Ein)
     variable Cos : Cosinus;   
     variable Sin : Sinus;
     variable SumSin : signed(3 downto 0);
 begin
     sumsin := (others => '0');
 ....
        for n in Sin'range loop
            SumSin := SumSin + Sin(n);                         
        end loop;
     end if;
     Aus_1 <= SumSin;    
  end process;