我正在使用 Verilog 和 ISE Xilinx 构建电梯。不幸的是,我遇到了一个错误:
unexpected reg (also register) expected end module.
但是,我确实需要寄存器。有人看出错误了吗?
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module user_ctrl
#(parameter FLOORS = 30,
FLOOR_BITS = 5)
(input wire CLK,
input wire RESET,
input wire [(FLOOR_BITS-1):0] CURRENT_FLOOR_IN, // cabin stage
input wire HALTED,
input wire [(FLOORS-1) :0] FLOOR_REQUEST, // floor button pressed
input wire MANUAL_DOOR_CLOSE_IN, // close button pressed
input wire MANUAL_DOOR_OPEN_IN, // open button pressed
input wire MANUAL_ALARM_IN, // alarm button pressed
output wire [(FLOOR_BITS-1):0] CURRENT_FLOOR_OUT, // forward to cabin display
output wire MANUAL_DOOR_CLOSE_OUT, // door close cmd
output wire MANUAL_DOOR_OPEN_OUT, // door open cmd
output wire MANUAL_ALARM_OUT, // user alarm
output wire [(FLOORS-1) :0] DESTINATIONS, // destinations
output reg [(FLOOR_BITS-1):0] CLEAR_FLOOR_BUTTON, // reset_button
output reg CLEAR_FLOOR_BUTTON_VALID); // validate reset_button
/* =============================INSERT CODE HERE======================================*/reg
reg [(FLOOR_BITS-1):0] floor; // sets the register
assign CURRENT_FLOOR_OUT = floor; //allocation of outputs and inputs
assign MANUAL_DOOR_CLOSE_OUT = MANUAL_DOOR_CLOSE_IN;
assign MANUAL_DOOR_OPEN_OUT = MANUAL_DOOR_OPEN_IN;
assign MANUAL_ALARM_OUT = MANUAL_ALARM_IN;
assign DESTINATIONS = FLOOR_REQUEST;
always @ (posedge HALTED)begin //to clear the buttons when elevator is stopped
floor = CURRENT_FLOOR_IN;
CLEAR_FLOOR_BUTTON_VALID = 1;
CLEAR_FLOOR_BUTTON = CURRENT_FLOOR_IN;
end
always @ (negedge HALTED)begin //to let the buttons enlighten when elavator is moving
CLEAR_FLOOR_BUTTON_VALID = 0;
end
/* ====================================================================================*/
endmodule
最佳答案
删除该行末尾的reg
。变化:
/* =============================INSERT CODE HERE======================================*/reg
至:
/* =============================INSERT CODE HERE======================================*/
关于verilog - 意外的 reg(也注册)预期结束模块,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/27555918/