我正在尝试实现如下内存模型,但我收到了这些警告消息:
assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};
|
ncelab: *W,BIGWIX (./sram.v,16|39): Memory index truncation.
Mem[Address] = Data;
|
ncelab: *W,BIGWIX (./sram.v,20|14): Memory index truncation.
这是我的代码:
// RAM Model
//
module sram (Address, Data, CS, WE, OE);
parameter AddressSize = 2592;
parameter WordSize = 32;
input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;
reg [WordSize-1:0] Mem [0:(1<<AddressSize)-1];
assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};
always @(CS or WE)
if (!CS && !WE)
Mem[Address] = Data;
always @(WE or OE)
if (!WE && !OE)
$display("Operational error in RamChip: OE and WE both active");
endmodule
“内存索引截断”是什么意思?
最佳答案
您可以使用 nchelp
获得有关任何 Cadence Incisive 警告的更详细帮助:
nchelp ncelab BIGWIX
ncelab/BIGWIX =
A memory is being indexed. The index expression has a width
greater than a machine word, which is typically 32 bits.
Only 32 bits are used. This truncation may result in
undesired behavior.
正如评论中提到的,您可能不希望地址输入信号为 2592 位宽,也不希望您的内存具有 (1<<2592) 个位置。
关于verilog - "Memory index truncation"是什么意思?,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/42943119/