arrays - 数组类型的 VHDL 赋值

标签 arrays types vhdl variable-assignment

考虑一种类型

type foo is array (0 downto 0) of std_logic_vector(7 downto 0);

例如,当我尝试创建此类型的常量值时,为什么会出现编译器错误。请注意,我只尝试过使用 Altera 的 Quartus II。

constant cFoo : foo := ( x"11" );

Error: VHDL Type mismatch error at [filename.vhd](line number): cFoo type does not match string literal.

但是,如果我的类型是,一切都可以

type foo is array (0 downto 0) of std_logic_vector(7 downto 0); 

给常量赋值的示例:

constant cFoo : foo := ( x"00", x"11" );

此外,考虑到我尝试用另一个常量分配索引 0。例如。

type foo is array (0 downto 0) of std_logic_vector(7 downto 0);
constant cBar : std_logic_vector(7 downto 0); 
constant cFoo : foo := ( cBar  );

编译器现在吐出的错误是:

VHDL error at [filename.vhd](line number): type of identifier "cBar" does not agree with its usage as "foo" type.

所以基本上它告诉我编译器没有意识到赋值是对索引 0 而是对数组类型的赋值。

如何让编译器知道该赋值仅针对索引 0?

最佳答案

IEEE 标准 1076 9.3.3 聚合,9.3.3.1 第 4 段:

Both named and positional associations can be used in the same aggregate, with all positional associations appearing first (in textual order) and all named associations appearing next (in any order, except that it is an error if any associations follow an others association). Aggregates containing a single element association shall always be specified using named association in order to distinguish them from parenthesized expressions.

带有 MCVE :

library ieee;
use ieee.std_logic_1164.all;

package ceefoo is
    type foo is array (0 downto 0) of std_logic_vector(7 downto 0);
    -- constant cFoo : foo := ( x"11" );
    constant cfoo:  foo := (0 => x"11");
    -- or
    constant cefoo: foo := (others => x"11");
end package;

您需要对单个元素使用命名关联。第一个示例指定索引 0,第二个示例指定任意元素。

上述小节第 3 段:

Each element association associates an expression with elements (possibly none). An element association is said to be named if the elements are specified explicitly by choices; otherwise, it is said to be positional. For a positional association, each element is implicitly specified by position in the textual order of the elements in the corresponding type declaration.

查看 BNF 很有帮助:

aggregate ::=
( element_association { , element_association } )

element_association ::=
     [ choices => ] expression

choices ::= choice { | choice }

choice ::=
     simple_expression
     | discrete_range
     | element_simple_name
     | others

关于arrays - 数组类型的 VHDL 赋值,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/38176962/

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