我正在尝试从具有启用功能的解码器在 verilog 中制作一个简单的多路复用器,但由于某种原因,当我尝试在启用锁定为 1 的多路复用器中使用解码器时,我收到错误。
module DECODER(out1, out2, out3, out4, A, B, enable);
`define NOT not #50
`define AND and #50
input A, B, enable;
output out1, out2, out3, out4;
wire notA, notB, val1, val2, val3, val4;
`NOT first (notA, A);
`NOT second (notB, B);
`AND firstEval(val1, notA, notB);
`AND secondEval(val2, notA, B);
`AND thirdEval(val3, A, notB);
`AND fourthEval(val4, A,B);
`AND firstOutput(out1, val1, enable);
`AND secondOutput(out2, val2, enable);
`AND thirdOutput(out3, val3, enable);
`AND fourthOutput(out4, val4, enable);
endmodule
module MUX (out, A, B, C, D, select1, select2);
`define AND and #50
`define OR or #50
output out;
input A,B,C,D,select1,select2;
wire selectA, selectB, selectC, selectD, firstOr, secondOr, andA, andB, andC, andD;
DECODER decoderModule(selectA, selectB, selectC, selectD, select1, select2,TRUE);
`AND checkA(andA, selectA, A);
`AND checkB(andB, selectB, B);
`AND checkC(andC, selectC, C);
`AND checkD(andD, selectD, D);
`OR firstStep(firstOr, andA, andB);
`OR secondStep(secondOr, firstOr, andC);
`OR throughPut(out, secondOr, selectD);
endmodule
module TEST;
reg A,B,C,D, select1, select2;
wire out;
initial
begin
A = 1; B = 1; C = 1; D = 1; select1 = 0; select2 = 0;
#300 A = 0;
#300 A = 1;
#300 select1 = 1;
#300 B = 0;
#300 B = 1;
#300 select2 = 1;
#300 D = 0;
#300 D = 1;
#300 select1 = 0;
#300 C = 0;
#300 C = 1;
end
MUX UUT(out, A,B,C,D,select1,select2);
initial
$monitor($time, ,out, , A,B,C,D,select1,select2);
endmodule
当我运行模拟时,出现以下错误:
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.1c/win32pe_edu/Mux.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'enable'. The port definition is at: C:/Modeltech_pe_edu_10.1c/win32pe_edu/Decoder.v(1).
任何有关如何解决此问题的帮助将不胜感激。我觉得我可能误解了 Verilog 如何使用静态值。
最佳答案
您尚未提供 TRUE
信号的定义。我已将您的 TRUE
替换为 1'b1
,现在模拟运行得更好:
DECODER decoderModule(selectA, selectB, selectC, selectD, select1, select2, 1'b1);
在大多数模拟器中,未声明的信号默认为 1'bx
。
或者,您可以在 MUX
模块中将 TRUE
声明为 wire
:
wire TRUE = 1'b1;
关于verilog - 在 Verilog 中使用静态值,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/12567680/