vhdl - vhdl中进程语句的顺序执行

Question

对于vhdl中的流程语句来说，流程语句内部的执行顺序是顺序的。我的问题是，请先看下面的代码，在process语句中的if语句中，a、b、c信号是同时赋值还是顺序赋值给它们的新值？

   process(clk) is
   begin
   if rising_edge(clk) then
   a <= b ;
   b <= c ;
   c <= a;
   end if;
   end process;

所以如果这是顺序的，我必须说在流程结束后，a 等于 b，b 等于 c，c 等于 b，因为我们在将 a 分配给 c 之前将 b 分配给 a。然而，这对于硬件来说似乎是不可能的。

Answer 1

构建包含您的流程的最小、完整且可验证的示例:

library ieee;
use ieee.std_logic_1164.all;

entity sequent_exec is
end entity;

architecture foo of sequent_exec is
    signal a:       std_ulogic := '1';
    signal b, c:    std_ulogic := '0';
    signal clk:     std_ulogic := '0';
begin
    CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if now > 200 ns then
            wait;
        end if;
    end process;
DUT:
    process(clk) is
    begin
    if rising_edge(clk) then
    a <= b ;
    b <= c ;
    c <= a;
    end if;
    end process;
end architecture;

我们看到 a、b 和 c 将值从一个移到另一个作为循环移位寄存器:

发生这种情况的原因与 VHDL 的仿真周期的运行方式有关。

参见 IEEE 标准 1076-2008

10.5 简单信号分配(10.5.1 通用):

A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals (see 14.7.2), schedules a force for one or more signals, or schedules release of one or more signals (see 14.7.3).

信号分配将新值排队等待信号更新。 10.5.2.2 Executing a simple assignment statement中描述了projected output waveform queue是如何操作的:

Evaluation of a waveform element produces a single transaction. The time component of the transaction is determined by the current time added to the value of the time expression in the waveform element. For the first form of waveform element, the value component of the transaction is determined by the value expression in the waveform element.

没有时间表达式的赋值是当前模拟时间。 (将发生增量循环 - 不提前模拟时间的模拟循环)。中描述的交易顺序 10.5.2.2 告诉我们相同模拟时间的旧交易被删除。

这意味着任何模拟时间都只有一个队列条目，并解释了为什么对特定信号的最后分配是导致事务的信号(并为进程敏感的信号生成事件)。

14.7 模型的执行包含有关仿真周期如何运行的信息(14.7.5 模型执行)。

14.7.5.1 一般:

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

14.7.5.3 Simulation cycle 描述了仿真周期，为了简单起见，这里使用 IEEE Std 1076-1993，不与 VHPI 操作混淆:

12.6.4 仿真周期

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

At the beginning of initialization, the current time, Tc, is assumed to be 0 ns.

The initialization phase consists of the following steps:

-- The driving value and the effective value of each explicitly declared signal are computed, and the current value of the signal is set to the effective value. This value is assumed to have been the value of the signal for an infinite length of time prior to the start of simulation.

-- The value of each implicit signal of the form S'Stable(T) or S'Quiet(T)is set to True. The value of each implicit signal of the form S'Delayed(T) is set to the initial value of its prefix, S.

-- The value of each implicit GUARD signal is set to the result of evaluating the corresponding guard expression.

-- Each nonpostponed process in the model is executed until it suspends.

-- Each postponed process in the model is executed until it suspends.

-- The time of the next simulation cycle (which in this case is the first simulation cycle), Tn, is calculated according to the rules of step f of the simulation cycle, below.

一个模拟周期包括以下步骤:

a. The current time, Tc is set equal to Tn. Simulation is complete when Tn= TIME'HIGH and there are no active drivers or process resumptions at Tn.
b. Each active explicit signal in the model is updated. (Events may occur on signals as a result.)
c. Each implicit signal in the model is updated. (Events may occur on signals as a result.)
d. For each process P, if P is currently sensitive to a signal S and if an event has occurred on S in this simulation cycle, then P resumes.
e. Each nonpostponed process that has resumed in the current simulation cycle is executed until it suspends.
f. The time of the next simulation cycle, Tn, is determined by setting it to the earliest of

1. TIME'HIGH,
2. The next time at which a driver becomes active, or
3. The next time at which a process resumes.
4. If Tn = Tc, then the next simulation cycle (if any) will be a delta cycle.

如果下一个模拟周期将是增量周期，则跳过此步骤的其余部分。否则，将执行每个已恢复但自上次恢复以来未执行的推迟进程，直到它挂起。然后根据步骤f的规则重新计算Tn。如果执行任何推迟的过程导致在当前模拟周期之后立即出现增量周期，则为错误。

信号值在进程执行期间不会改变。它们的更新在执行模拟周期的不同步骤中排队并应用。

回到-2008年:

1. 顺序语句，10.1 概述

The various forms of sequential statements are described in this clause. Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear.

我们看到顺序信号分配执行的顺序与更新顺序信号无关。