我正在模拟 CPU,并且使用高级模拟工具来完成此操作。 SystemC 是实现这些目的的一个很好的资源。我使用两个模块:
数据路径
内存
CPU 数据路径被建模为一个独特的高级实体,但是以下代码肯定会比任何其他解释更好:
以下是datapath.hpp
SC_MODULE(DataPath) {
sc_in_clk clk;
sc_in<bool> rst;
///
/// Outgoing data from memory.
///
sc_in<w32> mem_data;
///
/// Memory read enable control signal.
///
sc_out<sc_logic> mem_ctr_memreadenable;
///
/// Memory write enable control signal.
///
sc_out<sc_logic> mem_ctr_memwriteenable;
///
/// Data to be written in memory.
///
sc_out<w32> mem_dataw; //w32 is sc_lv<32>
///
/// Address in mem to read and write.
///
sc_out<memaddr> mem_addr;
///
/// Program counter.
///
sc_signal<w32> pc;
///
/// State signal.
///
sc_signal<int> cu_state;
///
/// Other internal signals mapping registers' value.
/// ...
// Defining process functions
///
/// Clock driven process to change state.
///
void state_process();
///
/// State driven process to apply control signals.
///
void control_process();
// Constructors
SC_CTOR(DataPath) {
// Defining first process
SC_CTHREAD(state_process, clk.neg());
reset_signal_is(this->rst, true);
// Defining second process
SC_METHOD(control_process);
sensitive << (this->cu_state) << (this->rst);
}
// Defining general functions
void reset_signals();
};
以下是datapath.cpp
void DataPath::state_process() {
// Useful variables
w32 ir_value; /* Placing here IR register value */
// Initialization phase
this->cu_state.write(StateFetch); /* StateFetch is a constant */
wait(); /* Wait next clock fall edge */
// Cycling
for (;;) {
// Checking state
switch (this->cu_state.read()) { // Basing on state, let's change the next one
case StateFetch: /* FETCH */
this->cu_state.write(StateDecode); /* Transition to DECODE */
break;
case StateDecode: /* DECODE */
// Doing decode
break;
case StateExecR: /* EXEC R */
// For every state, manage transition to the next state
break;
//...
//...
default: /* Possible not recognized state */
this->cu_state.write(StateFetch); /* Come back to fetch */
} /* switch */
// After doing, wait for the next clock fall edge
wait();
} /* for */
} /* function */
// State driven process for managing signal assignment
// This is a method process
void DataPath::control_process() {
// If reset signal is up then CU must be resetted
if (this->rst.read()) {
// Reset
this->reset_signals(); /* Initializing signals */
} else {
// No Reset
// Switching on state
switch (this->cu_state.read()) {
case StateFetch: /* FETCH */
// Managing memory address and instruction fetch to place in IR
this->mem_ctr_memreadenable.write(logic_sgm_1); /* Enabling memory to be read */
this->mem_ctr_memwriteenable.write(logic_sgm_0); /* Disabling memory from being written */
std::cout << "Entering fetch, memread=" << this->mem_ctr_memreadenable.read() << " memwrite=" << this->mem_ctr_memreadenable.read() << std::endl;
// Here I read from memory and get the instruction with some code that you do not need to worry about because my problem occurs HERE ###
break;
case kCUStateDecode: /* DECODE */
// ...
break;
//...
//...
default: /* Unrecognized */
newpc = "00000000000000000000000000000000";
} /* state switch */
} /* rst if */
} /* function */
// Resetting signals
void DataPath::reset_signals() {
// Out signals
this->mem_ctr_memreadenable.write(logic_sgm_1);
this->mem_ctr_memwriteenable.write(logic_sgm_0);
}
正如您所看到的,我们有一个处理 cpu 转换(更改状态)的时钟驱动进程和一个为 cpu 设置信号的状态驱动进程。
我的问题是,当我到达 ###
时,我希望指令被内存释放(您看不到指令,但它们是正确的,内存组件使用 in 和 连接到数据路径您可以在 hpp 文件中看到输出信号)。
内存让我“XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX”
,因为mem_ctr_memreadenable
和mem_ctr_memwriteenable
都设置为'0'
。
内存模块是为了成为即时组件而编写的。它是使用 SC_METHOD
编写的,其 sensitive
在输入信号上定义(包括读使能和写使能)。当 mem_ctr_memreadenable
信号为 '0'
时,内存组件获取 “XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX”
。
为什么是'0'
?我重置信号并将该信号设置为'1'
。我不明白为什么我一直使用 '0'
作为读取启用信号。
你能帮我吗? 谢谢。
最佳答案
我不是 SystemC 专家,但看起来这可能与常见的 VHDL 问题类似,即至少经过一个 delta 周期后信号才会更新:
this->mem_ctr_memreadenable.write(logic_sgm_1); /* Enabling memory to be read */
this->mem_ctr_memwriteenable.write(logic_sgm_0); /* Disabling memory from being written */
我的猜测:这两行和下一行之间没有时间经过:
std::cout << "Entering fetch, memread=" << this->mem_ctr_memreadenable.read() << " memwrite=" << this->mem_ctr_memreadenable.read() << std::endl;
所以内存还没有看到读取信号发生变化。顺便说一句,是否应该将其中一个 read()
调用附加到 mem_ctr_memwriteenable
- 两者似乎都处于可读状态?
如果你:
wait(1, SC_NS);
在这两点之间,事情是否有所改善?
关于systemc - SystemC 仿真应用程序中的信号处理问题,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/5650664/