VHDL - 设计库不包含单元

Question

我有以下架构:

architecture datapath of DE2_TOP is
begin
U1: entity work.lab1 port map (
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
);
end datapath;

我收到以下错误:Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work"does not contain primary unit "lab1" on the line : U1: 实体 work.lab1 端口映射 (。有人知道是什么原因造成的吗？

Answer 1

在编译 DE2_TOP 之前，您至少需要编译 lab1 的 entity