module fronter ( arc, length, clinic ) ;
input [7:0] arc;
output reg [7:0] length ;
input [1:0] clinic;
input en0, en1, en2, en3; // 11
// clock generator is here
g_cal A( en0) ;
g_cal B( en1) ;
g_cal C( en2) ;
g_cal D( en3) ;
always @( negedge arc, posedge clk )
case ( clinic )
2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23
2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24
2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25
2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26
default : { en3, en2, en1, en0 } = 4'bxxxx; // 27
endcase
// I am trying to change value of en to call corresponding intance with that
//corresponding en value
endmodule
module g_cal ( en ) ;
input en ;
// some other jobs, calling another instances after making some job
endmodule
当我编译时,编译器给我;
verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11: : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11: : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11: : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11: : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11: : en3 is declared here as wire.
segmentation fault
我该如何解决? 为什么报错?
编辑: 我已经解决了问题;
// I erased that line "input en0, en1, en2, en3; // 11"
// clock generator is here
g_cal A( 1'b0) ;
g_cal B( 1'b0) ;
g_cal C( 1'b0) ;
g_cal D( 1'b0) ;
always @( negedge arc, posedge clk )
/* erasing all those line
case ( clinic )
2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23
2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24
2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25
2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26
default : { en3, en2, en1, en0 } = 4'bxxxx; // 27
endcase
我将使用 if 和 else 结构,并用 1'b1*/调用相应的实例
// I am trying to change value of en to call corresponding intance with that
//corresponding en value
endmodule
最佳答案
您正在尝试分配给 input
(这很糟糕)。将 input en0, en1, en2, en3;
更改为 output reg en0, en1, en2, en3;
。 reg
是必需的,因为您要在过程 block (即 always
或 initial
)中分配给该变量。 “不是有效的左值”消息试图告诉您这一点。
此外,我假设 11、23、24 等是来自复制粘贴的杂散行号...
关于verilog - 不是有效的左值 - verilog 编译器错误,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/5636055/