syntax-error - 使用条件信号分配时的VHDL小错误(当…其他时)

Question

我目前正在开发一个将执行加法或减法运算的组件，具体取决于用户输入。现在，我正在一个处理将值分配给内部信号的过程，该信号将由我正在使用的内部组件使用。当我为b_in分配输入b或输入b的2的补码时，出现了一个问题。显示两个错误:

Error: COMP96_0015: addsub_16.vhd : (85, 17): ';' expected.
Error: COMP96_0046: addsub_16.vhd : (85, 41): Sequential statement expected.
The errors all reference to the line
b_in <= (b) when add_sub = '0' else (b_2scomp);
However when I placed this outside the process, no error occurred; only when it's inside the process. Can someone please help me why this is and what I can do to solve it?

另外，我知道通常在架构声明和架构的begin语句之间完成端口映射。我将它们放置在该过程之后的原因是，我需要确保b_in在其他组件可以使用它之前具有正确的信号。我不知道这是否是正确的方法，但我希望是这样。以防万一你们在想为什么我要这样子。谢谢

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity addsub_16 is
     port(
         c_in : in STD_LOGIC; 
         enable : in std_logic;
         reset : in std_logic;
         clk : in std_logic;
         add_sub : in STD_LOGIC;
         a : in STD_LOGIC_VECTOR(15 downto 0);
         b : in STD_LOGIC_VECTOR(15 downto 0);
         c_out : out STD_LOGIC;
         result : out STD_LOGIC_VECTOR(15 downto 0)
         );
end addsub_16;

architecture addsub_16 of addsub_16 is 

--Signal declarations to hold internal vectors a, b g, p, and carry
signal a_in : std_logic_vector(15 downto 0);        --Holds input a
signal b_in : std_logic_vector(15 downto 0);        --Holds input b if add_sub = 0. Otherwise, holds b_2scomp
signal b_2scomp : std_logic_vector(15 downto 0);    --Holds the 2s complement of b
signal prop_in : std_logic_vector(15 downto 0);     --Holds the propagate signals from CLAs
signal gen_in : std_logic_vector(15 downto 0);      --Holds the generate signals from CLAs
signal carry_in : std_logic_vector(15 downto 0);    --Holds the carry signal from carry_logic 
signal temp_result : std_logic_vector(15 downto 0); --Holds the temporary result to be driven out

--Component declarations 
component cla_4bit
    port (
        a, b : in std_logic_vector(3 downto 0);
        gen, prop : out std_logic_vector(3 downto 0)
        );
end component;

component carry_logic
    port (
        g, p : in std_logic_vector(15 downto 0);
        c_in : in std_logic;
        carry : out std_logic_vector(15 downto 0);
        c_out : out std_logic
    ); 
end component;

--Actual behavior of module
begin   

--b_in <= (b) when add_sub = '0' else (b_2scomp);

    process (clk, reset)
    begin 
        if reset = '0' then                 --At reset, everything is 0
            a_in <= (others => '0');
            b_in <= (others => '0');
            b_2scomp <= (others => '0');
            temp_result <= (others => '0');

        elsif (rising_edge(clk)) then       --Read in data to components on rising edge
            if enable = '1' then            --Only if enable is on
                a_in <= a;
                b_2scomp <= ((not b) + '1');
                b_in <= (b) when add_sub = '0' else (b_2scomp);             
            end if;
        elsif (falling_edge(clk)) then      --Drive out values on falling edge
            for i in 0 to 15 loop
                temp_result(i) <= a_in(i) xor b_in(i) xor carry_in(i);
            end loop;
            result <= temp_result;  
        end if;
    end process;

--portmapping of the components here. I don't think it'd be necessary to include them, but let me know if they are needed.

Answer 1

VHDL-2008之前的过程块中不允许使用三元运算符.. when .. else ..。

解决方案1:编写普通的if .. then .. else .. end if语句
解决方案2:在工具链中启用VHDL-2008支持
解决方案3:编写一个函数，让ite(if-then-else)执行三元运算。