compiler-errors - Verilog中的并发分配错误

Question

我的代码如下:

   module trapverilog(
        input CLK,
        input SIGNALP,
         input SIGNAL1,
         input SIGNAL2,
         input SIGNAL3,
         input SIGNAL4,
         input SIGNAL5,
         input SIGNAL6,
         input SIGNAL7,
         input X1,
         input X2,
         input X3,
         input X4,
         input X5,
         input X6,
         input X7,
         input SUMP,
         input SUM1,
         input SUM2,
         input SUM3,
         input SUM4,
         input SUM5,
         input SUM6,
         input SUM7, // OUT pins are mapped to SUM pins on board
        output reg OUTP,
         output reg OUT1,
         output reg OUT2,
         output reg OUT3,
         output reg OUT4,
         output reg OUT5,
         output reg OUT6,
         output reg OUT7
        );

reg[6:0] yregone;
reg[6:0] yregtwo;
reg[6:0] sum;
reg[6:0] SUM;
assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
reg[7:0] SIGNAL;
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
reg[6:0] x;
assign x = {X1. X2. X3. X4. X5, X6, X7};

always @(posedge CLK)
begin
    if (SIGNALP == 1)
    begin
        SIGNAL = SIGNAL * -1;
    end

    if (SUMP == 1)
    begin
        SUM = SUM * -1;
    end

    yregtwo = yregone;
    yregone = SIGNAL;

    if (yregtwo != 0)
    begin
        sum = ((yregone + yregtwo)*x/2) + SUM; //treats x as plain h, change if treated as h/2

        if (sum < 0)
        begin
            OUTP = 1;
        end

        OUT1 = sum[1];
        OUT2 = sum[2];
        OUT3 = sum[3];
        OUT4 = sum[4];
        OUT5 = sum[5];
        OUT6 = sum[6];
        OUT7 = sum[7];
    end
end

endmodule

产生错误

Target <SUM> of concurrent assignment or output port connection should be a net type.
Target <SIGNAL> of concurrent assignment or output port connection should be a net type.
Target <x> of concurrent assignment or output port connection should be a net type.

这些错误出现在定义SIGNAL，SUM和x的行上。我相信问题的部分原因是这些变量没有在always循环中定义，但是这样做会产生更多错误。我该怎么做才能解决此问题？

该代码用于在verilog中实现梯形积分方法。输入大量是因为我想并行输入数据，而不是串行输入，因为它更快。前缀为SIGNAL的所有输入都在SIGNAL变量中使用，前缀为X的所有输入都在x变量中使用，依此类推。输入名称末尾的P表示它是奇偶校验位。数字指示该位应在结果寄存器中的哪个位置。

Answer 1

您正在多个位置分配这些信号。你不能那样做。

assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
....
if (SIGNALP == 1)
begin
    SIGNAL = SIGNAL * -1;
end

if (SUMP == 1)
begin
    SUM = SUM * -1;
etc.

关于X:

assign x = {X1. X2. X3. X4. X5, X6, X7};
              ^   ^   ^   ^  Full stop????

另外，您应该在always @(posedge CLK)部分中使用非阻塞分配。