assembly - 英特尔 64 和 IA-32 |原子操作，包括获取/释放语义

Question

根据 Intel 64 and IA-32 Architectures Software Developer's Manual，LOCK 信号前缀“确保处理器在信号被断言时独占使用任何共享内存”。这可以是总线或缓存锁的形式。

但是——这就是我问这个问题的原因——我不清楚这个前缀是否也提供了任何内存屏障。

我正在多处理器环境中使用 NASM 进行开发，并且需要使用可选的获取和/或释放语义来实现原子操作。

那么，我是否需要使用 MFENCE、SFENCE 和 LFENCE 指令，或者这会是多余的吗？

Answer 1

不，不需要使用说明MFENCE, SFENCE and LFENCE关于 LOCK字首。MFENCE, SFENCE and LFENCE指令保证所有 CPU 内核中内存的可见性。例如 MOV指令不能与 LOCK 一起使用前缀，因此要确保所有 CPU 内核都可以看到内存移动的结果，我们必须确保将 CPU 缓存刷新到 RAM 并使用栅栏指令到达。
编辑:更多关于英特尔手册中锁定原子操作的信息:

LOCKED ATOMIC OPERATIONS

The 32-bit IA-32 processors support locked atomic operations on locations in system memory. These operations are typically used to manage shared data structures (such as semaphores, segment descriptors, system segments, or page tables) in which two or more processors may try simultaneously to modify the same field or flag. The processor uses three interdependent mechanisms for carrying out locked atomic operations:

• Guaranteed atomic operations

• Bus locking, using the LOCK# signal and the LOCK instruction prefix

• Cache coherency protocols that insure that atomic operations can be carried out on cached data structures (cache lock); this mechanism is present in the Pentium 4, Intel Xeon, and P6 family processors

These mechanisms are interdependent in the following ways. Certain basic memory transactions (such as reading or writing a byte in system memory) are always guaranteed to be handled atomically. That is, once started, the processor guarantees that the operation will be completed before another processor or bus agent is allowed access to the memory location. The processor also supports bus locking for performing selected memory operations (such as a read-modify-write operation in a shared area of memory) that typically need to be handled atomically, but are not automatically handled this way. Because frequently used memory locations are often cached in a processor’s L1 or L2 caches, atomic operations can often be carried out inside a processor’s caches without asserting the bus lock. Here the processor’s cache coherency protocols insure that other processors that are caching the same memory locations are managed properly while atomic operations are performed on cached memory locations.