vhdl - 如何在 VHDL 中初始化 std_logic_vector？

Question

我有一个 std_logic_vector(4096 downto 0) 信号，我想像下面这样初始化它:

architecture Behavioral of test is

    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type;
    ram(0) := "0010000000000100";   
    ram(1) := "0001000000000101";
    ram(2) := "0011000000000110";
    ram(3) := "0111000000000001";
    ram(4) := "0000000000001100";
    ram(5) := "0000000000000011";
    ram(6) := "0000000000000000";
    ram(4095 downto 7) := (others => (others => '0'));
    begin
   "some code"
end behavioral

出于某种原因，我需要用这些值初始化它(我无法将这些值分配给它，它必须被初始化) 有什么方法可以做到吗？我尝试了上面的代码，但它不起作用

Answer 1

ram 可以这样初始化:

architecture Behavioral of test is
    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type := (0 => "0010000000000100",
                              1 => "0001000000000101",
                              2 => "0011000000000110",
                              3 => "0111000000000001",
                              4 => "0000000000001100",
                              5 => "0000000000000011",
                              6 => "0000000000000000",
                              others => (others => '0'));
begin
  -- Concurrent code
end Behavioral;

但是您可能需要查看特定的 FPGA 和工具功能，看看是否应通过某种特定方式将初始化值赋予 RAM，以便综合工具可以正确映射它。