我正在尝试使用 Verilog 中的行为代码来模拟一个简单的 MIPS 处理器。我已经完成了代码的编写，但我到达了最后一步，我想在执行完 MIPS 指令后打破always block 。这是我的代码:
module MIPS_Processor(output reg[7:0] LEDs, input[7:0] Switches);
reg [31:0] memory[0:4095]; // 4K memory cells that are 8 bits wide
reg [31:0] code[0:1023]; // 1K memory cells that are 8 bits wide
reg [31:0] registers[0:31]; // 32 registers that are 32 bits wide
reg [31:0] PC; // The program counter
reg [31:0] instruction;
reg [5 :0] op;
reg [4 :0] rs;
reg [4 :0] rt;
reg [4 :0] rd;
reg [4 :0] shamt;
reg [5 :0] funct;
reg signed [15:0] immediate_offset;
reg [25:0] target;
reg [1:0] instruction_type; // 00 --> R | 01 --> I | 10 --> J | 11 --> EXTRA
reg [31:0] rs_value;
reg [31:0] rt_value;
reg [31:0] rd_value;
reg done = 0;
/*
Here we insert the code in the code array
*/
initial
begin
PC = 0;
end
always
begin
// 1. Fetch an instruction from memory
instruction = code[PC];
// 2. Increment the program counter register (by the instruction length)
PC = PC + 1;
// 3. Decode the instruction
/*
The instructions are:
6 5 5 5 5 6
_____________________________
or rd, rs, rt | 0 | rs | rt | rd | 0 | 0x25 |
6 5 5 16
_____________________________
ori rt, rs, immediate | 0xd | rs | rt | immediate |
6 5 5 5 5 6
_____________________________
and rd, rs, rt | 0 | rs | rt | rd | 0 | 0x24 |
6 5 5 16
_____________________________
andi rt, rs, immediate | 0xc | rs | rt | immediate |
6 5 5 16
_____________________________
beq rs, rt, offset | 4 | rs | rt | offset |
6 5 5 5 5 6
_____________________________
sub rd, rs, rt | 0 | rs | rt | rd | 0 | 0x22 |
6 5 5 5 5 6
_____________________________
add rd, rs, rt | 0 | rs | rt | rd | 0 | 0x20 |
6 5 5 16
_____________________________
addi rt, rs, immediate | 8 | rs | rt | immediate |
6 26
_____________________________
j target | 2 | target |
6 5 5 5 5 6
_____________________________
slt rd, rs, rt | 0 | rs | rt | rd | 0 | 0x2a |
6 5 5 16
_____________________________
lw rt, rs[offset] | 0x23 | rs | rt | offset |
6 5 5 16
_____________________________
sw rt, rs[offset] | 0x2b | rs | rt | offset |
::EXTRA INSTRUCTIONS::
6 5 21
_____________________________
input rs | 4 | rs | 0 |
6 5 21
_____________________________
output rs | 4 | rs | 1 |
*/
op[5:0] = instruction[31:26];
case(op)
0: /* R-type */
begin
rs = instruction[25:21];
rt = instruction[20:16];
rd = instruction[15:11];
shamt = instruction[10:6];
funct = instruction[5:0];
instruction_type = 2'b00;
end
1: /* END OF CODE */
begin
//$finish;
end
2: /* J-type */
begin
target = instruction[25:0];
instruction_type = 2'b10;
end
4: /* EXTRA */
begin
rs = instruction[25:21];
funct = instruction[20:0];
instruction_type = 2'b11;
end
default: /* I-type */
begin
rs = instruction[25:21];
rt = instruction[20:16];
immediate_offset = instruction[15:0];
instruction_type = 2'b01;
end
endcase
// 4. Fetch operands, if any, usually from registers
case(instruction_type)
2'b00: /* R-type */
begin
rs_value = registers[rs];
rt_value = registers[rt];
end
2'b01: /* I-type */
begin
rs_value = registers[rs];
end
2'b11: /* EXTRA */
begin
if(funct == 1) rs_value = registers[rs];
end
endcase
// 5. Perform the operation
case(instruction_type)
2'b00: /* R-type */
begin
case(funct)
2'h20: /* add rd, rs, rt */
begin
rd_value = rs_value + rt_value;
end
2'h22: /* sub rd, rs, rt */
begin
rd_value = rs_value - rt_value;
end
2'h24: /* and rd, rs, rt */
begin
rd_value = rs_value & rt_value;
end
2'h25: /* or rd, rs, rt */
begin
rd_value = rs_value | rt_value;
end
2'h2a: /* slt rd, rs, rt */
begin
rd_value = rs_value < rt_value? 1 : 0;
end
endcase
end
2'b01: /* I-type */
begin
case(op)
4: /* beq rs, rt, offset */
begin
if(rs_value < rt_value) PC = immediate_offset;
end
8: /* addi rt, rs, immediate */
begin
rt_value = rs_value + immediate_offset;
end
1'hc: /* andi rt, rs, immediate */
begin
rt_value = rs_value & immediate_offset;
end
1'hd: /* ori rt, rs, immediate */
begin
rt_value = rs_value | immediate_offset;
end
2'h23: /* lw rt, rs[offset] */
begin
rt_value = memory[rs + immediate_offset];
end
2'h2b: /* sw rt, rs[offset] */
begin
memory[rs + immediate_offset] = rt_value;
end
endcase
end
2'b10: /* J-type */
begin
case(op)
2: /* j target */
begin
PC = target;
end
endcase
end
2'b11: /* EXTRA */
begin
case(funct)
0: /* input rs */
begin
rs_value[7:0] = Switches;
end
1: /* output rs */
begin
LEDs = rs_value[7:0];
end
endcase
if(funct == 1) rs_value = registers[rs];
end
endcase
// 6. Store the results
case(instruction_type)
2'b00: /* R-type */
begin
registers[rd] = rd_value;
end
2'b01: /* I-type */
begin
case(op)
8: /* addi rt, rs, immediate */
begin
registers[rt] = rt_value;
end
1'hc: /* andi rt, rs, immediate */
begin
registers[rt] = rt_value;
end
1'hd: /* ori rt, rs, immediate */
begin
registers[rt] = rt_value;
end
2'h23: /* lw rt, rs[offset] */
begin
registers[rt] = rt_value;
end
endcase
end
2'b11: /* EXTRA */
begin
if(funct == 0) registers[rs] = rs_value;
end
endcase
end
endmodule
我尝试了 $finish 但它不起作用:
1: /* END OF CODE */
begin
//$finish;
end
那么，我怎样才能打破always block 呢？或者我应该使用其他东西来代替？
最佳答案
always 不是 while 循环。请参阅wikipedia's entry on verilog 。由于您没有任何像 #10 这样的临时消耗语句，它将连续执行您的代码，就像 C 中意外的 while 1 block 一样。要么这样，要么编译器可能会只需将您的代码标记为错误即可。但是，在代码中使用 #10 只是一种 hack。您确实想让您的 always block 仅执行每个 posege clk 或创建适当的 pipline。因此，您需要一个启用信号，并且需要将您的always block 设置为@(thoughtge clk)，以安排该 block 在每个时钟滴答而不是永远发生，而不需要提前模拟时间。
关于loops - 如何在Verilog中打破always block ？，我们在Stack Overflow上找到一个类似的问题： https://stackoverflow.com/questions/9896701/