c - ARM Cortex-M 内存访问

Question

来自Cortex-M0+ Devices Generic User Guide关于内存区域-

2.2.1. Memory regions, types and attributes

Strongly-ordered:

The processor preserves transaction order relative to all other transactions.

并且-

Address range: 0xE0000000- 0xE00FFFFF

Memory region: Private Peripheral Bus

Memory type: Strongly- ordered

Description: This region includes the NVIC, System timer, and System Control Block. Only word accesses can be used in this region.

现在，来自CMSIS documentation -

#define __DMB()

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

根据上述信息，似乎在访问0xE0000000-0xE00FFFFF内存地址范围的代码中，例如，NVIC Controller 和SysTick 配置寄存器，我不需要使用__DMB，因为它实际上是由硬件执行的。

例如，如果我们查看 __NVIC_EnableIRQ-

/**
 \brief   Enable Interrupt
 \details Enables a device specific interrupt in the NVIC interrupt controller.
 \param [in]    IRQn  Device specific interrupt number.
 \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
    if ((int32_t)(IRQn) >= 0)
    {
        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
    }
}

它不包含 __DMB() (也没有 __DSB() 和 __ISB())，所以如果我启用中断 X，然后启用中断 Y，操作之间没有障碍 -

NVIC_EnableIRQ(X); /* Note: __NVIC_EnableIRQ is defined as NVIC_EnableIRQ */
NVIC_EnableIRQ(Y);

是否 promise 硬件不会重新排序内存访问，并在中断 Y 之前启用中断 X(假设编译器确实将函数实现为内联)？

Answer 1

Is it promised that the HW will enable interrupt X before interrupt Y

是的。编译器不得优化写入访问或更改顺序 - ISER 在 CMSIS header 中声明为 volatile 。

请注意，与较大的同类产品不同，Cortex-M0+ 没有写入缓冲区。