c - 为什么程序对 Xilinx 定时器驱动程序中的只读定时器中断状态寄存器执行写访问

Question

在 Xilinx 板的 Linux 内核版本 3.2.52 中，

https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/arch/arm/mach-zynq/timer.c?id=refs/tags/v3.2.53

定时器驱动程序中有对只读寄存器的写过程。 在第123行，为什么这个函数对只读寄存器(XTTCPSS_ISR_OFFSET)执行写访问？

static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &xttcpss_clockevent;
struct xttcpss_timer *timer = dev_id;

/* Acknowledge the interrupt and call event handler */
__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), <--- this
        timer->base_addr + XTTCPSS_ISR_OFFSET);

evt->event_handler(evt);

XTTCPSSS_ISR_OFFSET 在 L.63 中定义。

#define XTTCPSS_ISR_OFFSET      0x54 /* Interrupt Status Reg, RO */

这是一种特殊的技术吗？

Answer 1

这个已经在大约一年前用这个补丁删除了，它告诉你写的原因:

Refs: v3.8-rc3-47-gaf7f032
Author:     Soren Brinkmann <soren.brinkmann@xilinx.com>
AuthorDate: Wed Dec 19 10:18:37 2012 -0800
Commit:     Michal Simek <michal.simek@xilinx.com>
CommitDate: Mon Jan 28 13:27:21 2013 +0100

    arm: zynq: timer: Remove unnecessary register write

    Acknowedging an interrupt requires to read the interrupt register
    only. The write was only required to work around a bug in
    the QEMU implementation of the TTC, which is fixed.

    Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
    Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
    Tested-by: Josh Cartwright <josh.cartwright@ni.com>
---
 arch/arm/mach-zynq/timer.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 570491d..f1d224b 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -121,8 +121,7 @@ static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
        struct xttcps_timer *timer = &xttce->xttc;

        /* Acknowledge the interrupt and call event handler */
-       __raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET),
-                       timer->base_addr + XTTCPS_ISR_OFFSET);
+       __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);

        xttce->ce.event_handler(&xttce->ce);